1. Field of the Invention
The present invention relates to buffer circuits and more particularly to an output buffer circuit with improved noise immunity and speed.
2. Description of Related Art
FIGS. 1A and 1B show two prior art output buffer circuits. FIG. 1A shows an output buffer circuit 5 wherein both the pull-up transistor M11 and the pull-down transistor M12 are NMOS transistors. M11 has its drain connected to the power supply Vcc, its gate connected to lead 13 and its source connected to node 12. M12 has its drain connected to node 12, its gate connected to lead 14 and its source connected to the ground Vss. The source of M11 and the drain of M12 are connected to the output terminal Q1 of circuit 5. Capacitor C1 at the output terminal Q1 represents the output load which the buffer circuit 5 drives.
To drive the output terminal Q1 high, the buffer driver circuit 11 causes lead 13 to go high (i.e., Vcc) thereby turning on M11, and causes lead 14 to go low (i.e., Vss) thereby turning off M12. With the drain and gate of M11 at Vcc, output terminal Q1 is raised to Vcc minus a threshold voltage (VT). Assuming Vcc to be 5 V and the threshold voltage of M11 to be 1 V, the output terminal Q1 reaches a high voltage level of 4 V.
To drive the output terminal Q1 low, the buffer driver circuit 11 causes lead 13 to go low thereby turning off M11, and lead 14 to go high thereby turning on M12.
One advantage of circuit 5 is that because the high voltage level on output terminal Q1 is Vcc minus VT (or 4 V), the high to low transition on the output terminal Q1 is faster as compared to the case wherein the output terminal is driven to full Vcc (or 5 V). Further, the amount of charge discharged into Vss during the high to low transition is lower. This in turn reduces the amount of noise generated on Vss. In devices with multiple output buffer circuits wherein multiple output capacitances can be discharged to Vss at the same time, the cumulative effect of the reduction in the amount of charge discharged into Vss is a significant noise reduction on Vss.
One disadvantage of circuit 5 is slow low to high transition at the output terminal Q1. Initially, when the output terminal Q1 starts to rise, M11 has 5V across both its gate to source and drain to source. However, as the output terminal Q1 rises, the voltage across both the gate to source and drain to source reduce, causing M11 to rapidly become weak. Thus, the output terminal Q1 rises slowly after an initial brief rapid rise.
Circuit 50 in FIG. 1B is identical to circuit 5 in FIG. 1A except that a PMOS transistor M110 is used as the pull-up transistor. To pull the output terminal Q10 high, the gates of transistors M110 and M120 at the respective leads 130 and 140 are pulled low (to 0 V). Since M110 is a PMOS transistor, with 0 V at its gate, the output terminal Q10 is pulled up to the full Vcc level. To pull the output terminal Q10 low, the gates of M110 and M120 are pulled high.
The advantage of circuit 50 is that the low to high transition at the output terminal Q10 is fast. This is because the PMOS transistor M110 has -5 V across its gate to source throughout the transition. However, this circuit suffers from the following two disadvantages: 1) a high to low transition is slower since the transition is made from full Vcc as opposed to Vcc minus VT, and 2) more noise is generated on Vss since a greater amount of charge is discharged into Vss during the high to low transition.
Accordingly, there is a need for an output buffer circuit providing fast output transitions with low ground noise.